Semiconductor integrated circuits have substantially increased in density in the past decade. However, there is an increasing demand for even greater complexities, higher switching speeds and smaller devices for new applications such as microprocessors, minicomputers or the like. It is known that for realizing very high performance transistors, that the transistor device elements must be made more shallow and smaller in size. Two major elements that have been made smaller are the depth of the emitter-base junction and the base width between the emitter-base junction and the base-collector junction. For example, in the U.S. Pat. Nos. 4,236,294 to N. G. Anantha et al and 4,157,269 to T. H. Ning et al and both assigned to the same assignee as the present patent applications there are described methods and resulting structures for forming high performance bipolar transistor integrated circuits. In these patents there are shown methods to form shallow emitters and narrow base width bipolar devices. These patents are exemplary of the use of polycrystalline silicon as the extrinsic base source of P type dopant and the contact for the base region of the bipolar integrated circuit transistor.
The state of the art process technology places present current switch circuit performance in the order of more than about 400 to 500 pico seconds. Further progress in high performance mainframe computers requires delays of the order of two times smaller. Improvements in Very Large Scale Integration (VLSI) high performance devices to obtain such speeds necessitates shallow emitter base profiles which decrease emitter diffusion capacitance; tighter design rules which allow increased packing density and thus reduced interconnect parasitics; and independent control of conductivity properties of intrinsic and extrinsic base allows decreasing base resistance. These process enhancements will allow circuit performance at the level of less than about 300 pico seconds.
It is an object of this invention to describe a now process for making high performance bipolar transistors which allow for both the reduction of the extrinsic base resistance and the emitter area.
It is a further object of this invention to provice a method which allows independent control of the intrinsic and extrinsic base resistances thus allowing vertical scaling of the intrinsic active device without an increase in intrinsic base resistance.